In a conventional operational amplifier, high slew rate is achieved via increasing the current of a differential input pair or decreasing compensation capacitance. However, increasing the current of a differential input pair will increase static current consumption, and decreasing compensation capacitance will deteriorate the stability of the operational amplifier.
Another conventional method to achieve a high slew rate, wherein error amplifiers are utilized to drive a complementary common-source output stage, is shown in FIG. 1. This apparatus includes: an operational amplifier 11, two error amplifiers 12 and 13, a PMOS (P-type Metal Oxide Semiconductor) FET (Field Effect Transistor) 14 and an NMOS (N-type Metal Oxide Semiconductor) FET 15. The error amplifiers 12 and 13 are used to control the PMOS FET 14 and NMOS FET 15 of the output stage, which is implemented via coupling the inverting terminals of the error amplifiers 12 and 13 to the output terminal of the operational amplifier 11 and coupling the non-inverting terminals to an output node Vout. Further, a negative feedback loop comprising the error amplifier 12 and the PMOS FET 14 and a negative feedback loop comprising the error amplifier 13 and the NMOS FET 15 are used to control the push-pull common source output stage formed by a PMOS FET 14 and a NMOS FET 15.
In the conventional high slew rate operational amplifier, when the output voltage V0 is smaller than the output voltage V1 of the operational amplifier 11, the output voltage V2 of the error amplifier 12 will therefore decrease so as to enhance the conductivity of the PMOS FET 14, and the output voltage V3 of the error amplifier 13 will therefore decrease so as to attenuate the conductivity of the NMOS FET 15 or even turn off the NMOS FET 15. Consequently, the PMOS FET 14 will push (or source) current to the output node Vout. When the output voltage V0 is greater than the output voltage V1 of the operational amplifier 11, the output voltage V2 of the error amplifier 12 will therefore increase so as to attenuate the conductivity of the PMOS FET 14 or even turn off the PMOS FET 14, and the output voltage V3 of the error amplifier 13 will therefore increase so as to enhance the conductivity of the NMOS FET 15. Consequently, the NMOS FET 15 will pull (or sink) current from the output node V0.
When the output voltage V0 is equal to the output voltage V1 of the operational amplifier 11, the output voltage V2 of the error amplifier 12 will bias the PMOS FET 14 with a static current Ib, and the output voltage V3 of the error amplifier 13 will bias the NMOS FET 15 with a exactly the same static current Ib. In other words, when the input is equal to the output, the PMOS FET 14 and NMOS FET 15 operate at the predetermined DC bias condition.
The abovementioned architecture is generally used to drive a heavy load, such as a circuit of small resistances or large capacitances. The aspect ratio of the PMOS FET 14 and NMOS FET 15 thereof has to be very large, making this apparatus area inefficient. Besides, offset voltage, layout symmetry, bandwidth and noise have to be taken into consideration in the design of an error amplifier. Therefore, this apparatus has a complicated circuit structure, which occupies a great area of the chip and consumes considerable static power.